1. Field of the Invention
The present invention relates to a display device, and more particularly to a technique which is effectively applicable to a display device having a shift register circuit.
2. Description of the Related Art
For example, in an active-matrix-type liquid crystal display device which uses thin film transistors (TFT) as active elements, on a liquid-crystal-side surface of one substrate out of substrates which are arranged to face each other in an opposed manner with liquid crystal sandwiched therebetween, pixel regions are formed. Each pixel region is surrounded by two scanning lines which extend in the x direction and are arranged parallel to each other in the y direction and two video lines which extend in the y direction and are arranged parallel to each other in the x direction. The pixel region includes the thin film transistor (TFT) which is operated in response to the supply of a scanning signal from the scanning line.
The liquid crystal display device includes a scanning line driver circuit which supplies a scanning signal to the respective scanning lines, and a video line driver circuit which supplies a video signal to the respective video lines, and these driver circuits respectively include a shift register circuit.
On the other hand, there has been also known a polysilicon-type liquid crystal display device in which a semiconductor layer of a thin film transistor which constitutes the above-mentioned active element is made of polycrystalline silicon (polysilicon). In such a polysilicon-type liquid crystal display device, the thin film transistor (for example, MIS transistor) which constitutes the scanning line driver circuit and the video line driver circuit is also formed on the above-mentioned surface of one substrate in the same step as the thin film transistor which constitutes the active element.
A liquid crystal display device which includes a single-channel (n-MOS) shift register circuit as the scanning line driver circuit is disclosed in JP-A-2002-215118 (patent document 1) and JP-A-2006-10784 (patent document 2), for example.
FIG. 9 is a circuit diagram showing the circuit constitution of the single-channel (n-MOS) shift register circuit disclosed in the above-mentioned patent document 1.
The manner of operation of the shift register circuit shown in FIG. 9 is explained hereinafter.
(1) When a start pulse ((ΦDIN) is at a High level (hereinafter, referred to as H level), a transistor (NMT3) is turned on, and a reference voltage (VSS) is inputted to a gate of a transistor (NMT2) and hence, the transistor (NMT2) is turned off. Accordingly, a node (N1) assumes an H level (in a strict sense, VH−Vth) via a transistor (NMT1) in diode connection. Here, symbol VH indicates an H level voltage of a first drive clock (Φ1) and a second drive clock (Φ2), and symbol Vth indicates a threshold voltage of the transistor (NMT*). Further, when the node (N1) assumes the H level, a transistor (NMT7) is turned on, and the reference voltage (VSS) is inputted to a gate of a transistor (NMT6) and hence, the transistor (NMT6) is turned off. Thereafter, the start pulse ((ΦIN) assumes a Low level (hereinafter, referred to as L level).
(2) Next, when the second drive clock ((Φ2) assumes an H level, a node (N2) assumes an H level via a transistor (NMT4). Accordingly, a voltage of the node (N1) is further increased due to a bootstrap effect generated by a capacitive element (CB1). Then, the second drive clock having no voltage drop is outputted to the node (N2), and this second drive clock becomes a shift output (OUT1). Here, the transistor (NMT7) maintains an ON state, and the transistor (NMT6) maintains an OFF state.
Further, when the node (N2) assumes an H level, a transistor (NMT5) is turned on and hence, a node (N3) also assumes an H level (in a strict sense, VH−Vth). Then, when the node (N3) assumes an H level, a transistor (NMT11) is turned on, and the reference voltage (VSS) is inputted to a gate of a transistor (NMT15) and hence, the transistor (NMT15) is turned off.
(3) Next, when the first drive clock (Φ1) assumes an H level, a node (N4) assumes an H level via a transistor (NMT8). Accordingly, a voltage of the node (N3) is further increased due to a bootstrap effect generated by a capacitive element (CB2). Then, the first drive clock having no voltage drop is outputted to the node (N4), and this first drive clock becomes a shift output (OUT2). Here, the transistor (NMT11) maintains an ON state, and the transistor (NMT15) maintains an OFF state.
Further, when the node (N4) assumes an H level, a transistor (NMT9) is turned on and hence, a node (N6) also assumes an H level (in a strict sense, VH−Vth). Then, when the node (N6) assumes an H level, a transistor (NMT16) is turned on, and the reference voltage (VSS) is inputted to a gate of a transistor (NMT20) and hence, the transistor (NMT20) is turned off.
Further, when the node (N4) assumes the H level, a transistor (NMT10) is also turned on and hence, the node (N5) also assumes an H level (in a strict sense, VH−Vth). Then, when the node (N5) assumes the H level, the transistor (NMT2) is turned on, and the node (N1) assumes the reference voltage (VSS).
Operations similar to the above-mentioned operations are repeatedly performed thereafter.